In the conventional method of accessing memory arrays (including flash memory arrays), whether it be a read or write operation, each operation is performed sequentially, meaning that an operation has to be completed before the start of the next read or write operation. In performing an operation to access a memory array, the given data address is first decoded and the decoded address is provided to the memory array for fetching the data or storing the data. Because each of the decoding and accessing steps are done in a sequential manner, these architectures of the prior art memory arrays do not lend themselves to faster throughputs necessary for modern day high-speed memory access and throughput requirements.
Therefore, it would be desirable to have a method and memory architecture conducive to high-speed memory throughput not limited to the sequential speed of each memory access.